Time-interleaved Analog-to-Digital Converters (TIADC) have received considerable attention in the recent past in applications that require very high sample rates, i.e., sample rates that cannot be achieved by a single present-day ADC. In a TIADC employing M ADCs, each ADC operates at Fs/M where Fs is the sampling rate of the TIADC. The output from each TIADC is combined at Fs using a commutator to produce a sample rate converter operating at Fs. Ideally, the slower ADCs should have the same offset, gain, and uniform sample instants. In practice, however, due to component mismatches, this requirement is difficult to achieve. The differences in the offset values of the slower ADCs produce tones at kFs/M, for k=0,1,2, . . . , irrespective of the input signal. The differences in the gain values of the ADCs produce spurious (or unwanted) signals at ±Fin+kFs/M, for k=1,2, . . . , where Fin is any frequency of the input signal. Similarly, the non-uniformity of sampling instants of each ADC with respect to the TIADC sampling frequency produce spurious signals at exactly the same location as the spurs due to gain mismatch. However, the spurs due to the sample-time mismatch are orthogonal to those due to the gain mismatch. Consequently, the resulting spurious signals due to offset, gain and sample-time mismatches degrade the performance of the TIADC system significantly, thus making the estimation and correction of these errors imperative to improve performance.